Able to make sub-micron thin film by Sputter or PECVD.
i-line & Broad band 1X Aligner.
Back & Front side align.
4”, 8”, 12” Process.
EP bath for Ni, Ni alloy, Au, Cu, Sn, Rh.
Polishing process for Ceramic & Silicon wafers.
Wet etch process.
Dry(ICP) etch process.
Multi-layer simultaneous production
Channel sharing with multi-layer wiring
Enables high para probe card sharing with multi-layer wiring
Improved flatness of multi-layer
Interconnect Technology with Conductive Ink
Electrical Connection by metal sintering
Small Size Via : ≥ 15um
C4 Pad Pitch : ≥ 30um
Low Contact Force : 1.45gf (@Force at OD 75um)
High CCC : 1,500mA (@ISMI)
Available Pitch : ≥ 50um
Long life cycle : ≥ 1,000,000TD
High reliability performance with new Ni alloy plating technology
MEMS Vertical Structure
Various probe solution for Cu-Pillar Bumps & BGA
High Aspect Ratio : 6.5:1
Guaranteed thermal reliability : No Crack, No Delamination
(@TSCT, Reflow, Floating)
Stable electrical characteristic : Resistance change within ±10%
(@Bare Board Test)